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Subject Code : EN0720
Assignment Task:

Task:

Objectives: 

To create SystemVerilog (SV) design source descriptions for the various component parts of a Monitoring System comprising an Analogue-to-Digital Converter, Asynchronous Serial  Data Transmitter, and Receiver along with a display. 

To incorporate an IP (Intellectual Property) module into the design using customization and interfacing. 

• To perform simulations of individual design modules using SV test-modules and the  Vivado® Simulator. 

To perform simulations of the complete Monitoring System top-level module using an SV  test-module and the Vivado® Simulator. 

Synthesise and Implement the Monitoring System, targeting a Field Programmable Gate  Array development board (Artix-7 FPGA on Digilent® Basys3® development board).  • Demonstrate the operation of the FPGA implementation of the Monitoring System using the  Basys3® development board by means of a so-called ‘hardwired loop-back’ test.

 

Assignment 1 - Description of the Monitoring System 

Figure 1, below, shows a simplified block diagram of the Monitoring System, and figure 2 shows the corresponding physical layout of the Basys3 development board. 

The system is driven by a 100MHz crystal clock and an active-high reset push button, when the latter is pressed, the entire system is reset. The main functional blocks that make up the system  are shown in figure 1: 

i. XADC – built-in analog-to-digital Converter that can be instantiated from the IP library.  The analogue input voltage range is 0.0 to +1.0 Volts. 

ii. XADC Controller – responds to manual or timer generated pulses initiating an ADC  conversion, it produces the required control signals for the XADC and interfaces with the transmitter. 

iii. Transmitter – after each conversion, the 12-bit result is transmitted over an asynchronous serial data link as an individual character. 

iv. Receiver – receives the asynchronous character from the transmitter and displays the value on the 7-segment display. 

This assignment involves the design, verification and implementation of the Monitoring System  using a Field Programmable Gate Array (FPGA) device, this is achieved through a series of  guided tasks.'

Simplified block diagram of the Monitoring System

 

 

Figure 2 – Physical layout of the Monitoring System on Basys3 Board 

Figure 3, below, is a more detailed internal block diagram of the Monitoring System. The shaded blocks shown in figure 3 are implemented within the Artix-7 FPGA device. The 4-digit, 7-segment  display, R-2R ladder network Digital-to-Analogue Converter, clock generator, and various buttons and switches are located on the Basys3 board and connected to specific FPGA pins as specified in the ‘*.xdc’ (Xilinx Design Constraint) file. 

Figures 3a and 3b show the left- and right-hand sides of the system in more detail. 

Figures 3 (3a and 3b) shows the FPGA pin designators next to each input/output terminal, for example, the transmitter output ‘TxData’ is allocated FPGA pin ‘A14’, and this, in turn, is connected to header connector ‘JB1’, as shown in figure 2. 

The R-2R DAC, shown at the top left-hand corner of figure 3, is an external plug-in ‘PMOD’ module. This is used to produce a test voltage for input to the XADC, the value of which is set by the eight sliding switches ‘SW0..7’. When testing the Basys3 board it is important to ensure the switches are set such that the test voltage is within the range of the XADC unipolar input, i.e. 0.0  to +1.0 Volts. 

A careful study of all three figures (3, 3a, and 3b) will reveal that interconnecting signal names and module port names have been matched throughout the design (see red box in figure 3a), with one or two exceptions. This allows the use of the SystemVerilog automatic port connection feature,  considerably shortening and simplifying the source descriptions. 

 

 Physical layout of the Monitoring System on Basys3 Board 

 

 

Task 1 – Create a SV source description of the ‘RxSysRTL’ module 

Figure 5 shows the ASM chart and other details relating to the receiver module ‘RxSysRTL’. The figure shows the behavior of the module in the form of an ASM chart, along with a symbolic representation and the main internal registers. The internal signal named ‘Start’ is derived from the serial data input ‘RxIn’ such that a single clock-pulse-length pulse is produced on ‘Start’ each time  ‘RxIn’ undergoes a logic-1 to logic-0 transition (Refer to figure 3, the ‘MP’ circuit plays a similar role). 

At the bottom right-hand corner of figure 5, a logic circuit is included to illustrate the operation of the ‘Parity’ error output (parity_error). The system enters state ‘s5’ once a complete serial data character has been received (the shift register (SR) is transferred to the buffer register (BR) in the previous state, ‘s4’) and a logic-1 is transferred to the ‘buffer_full’ output. The ‘buffer_full’ signal enables the parity circuit flip-flop to load a value from the respective logic shown on the diagram (Exclusive-OR and Nand gate).  

In the event of a parity error, the ‘parity_error’ output flag remains high until, either a master reset  occurs, or the next data character is received 

The parallel data output of the receiver module ‘data_rx’ is 16-bits in length, in order to drive the 4- digit hexadecimal display logic directly. The data value received from the transmitter occupies the lower bits of this output bus. 

The receiver cannot receive another serial data character until the buffer is read, i.e. the  ‘read_buffer’ input is asserted. 

Appendix A contains a listing for the transmitter module ‘TxSysRTL’, in the form of a  SystemVerilog register transfer level (RTL) description. Appendix B contains the corresponding  ASM chart for the transmitter. 

Using the information provided in appendices A and B, along with figure 5, create a complete  Register Transfer Level (RTL) SV source description for the receiver module, saving it in a text file named ‘RxSysRTL.sv’. The receiver module is to have an identical set of parameter declarations when compared to the transmitter module. The source file can be created within the Xilinx  Vivado® software, alternatively, Notepad++ could be used. 

Include a full listing of the ‘RxSysRTL’ module in your report, presented in a style consistent with that used in Appendix A (consolas font, reserved words bold, comments in italics with appropriate use of indentation).

 

Task 3 – Add the remaining sources to the Vivado RTL project Go to the eLearning portal and locate the ‘XADC Display (SV)’ item in the ‘Week 4’ folder of module KD7020(EN0720), as shown in the image below. 

 Physical layout of the Monitoring System on Basys3 Board 

 

Task 4.1 – Modify the ‘XADC_Controller_tx’ module 

Page 28 of the ‘XADC_Display_SV_2019.pdf’ document shows the existing ASM chart for the control block ‘XADC_Controller’. As shown in figure 3 (3a) above, an additional output, named  ‘write’, is required to drive the ‘write’ input of the transmitter module ‘TxSysRTL’.

The ‘write’ signal is to be asserted during an additional state named ‘TRANS’ that is entered unconditionally from the ‘GET_DATA’ state. Note that ‘write’ is a direct output that occurs during state ‘TRANS’, it is not a register transfer. 

The added state ‘TRANS’ leads unconditionally back to the ‘WT_TRIG’ state. 

Figure 3a also shows an additional modification of the ‘XADC_Controller_tx’ is required. The ‘data’  output port is 12-bits rather than 16-bits wide. In the ‘GET_DATA’ state, the most-significant 12- bits of the XADC output data (do_out) is to be transferred to the ‘data’ output register. 

Draw a modified ASM chart for the ‘XADC_Controller_tx’ module, showing the additional state and modified register transfer described above. Include a copy of the modified ASM chart in your report. 

 

 

Task 4.2 – Complete the top-level design module source description  

‘XADC_TxSys_RxSys_Display.sv’. 

Compare figure 3 on page 4 of this document (XADC_TxSys_RxSys_Display) with the diagram on page 2 of the ‘XADC_Display_SV_2019.pdf’ document (XADC_RTL_Display). The major difference between the two systems is the addition of the bit-serial transmitter and receiver modules to the design. 

Study figure 3 carefully and make the necessary modifications to the SV source file  ‘XADC_TxSys_RxSys_Display.sv’, adding the extra input/output ports and internal signals associated with the communications channel along with the instantiations of the ‘TxSysRTL’ and  ‘RxSysRTL’ modules. Add a continuous assignment to describe the multiplexer that selects between the timer-generated and manual trigger pulses (‘Auto_Man’ input). Make use of the SV  automatic port connection feature in order to shorten and simplify the net-list. 

Include a full listing of the modified ‘XADC_TxSys_RxSys_Display.SV’ module source in your report, presented in a style similar to that used in Appendix A (Consolas font, reserved words bold, comments in italics with appropriate use of indentation). Do not use a screen copy of the listing as it appears within the Vivado text editor. 

 

Task 5 – Modify the simulation test-module source file ‘testbench.sv’. 

The Verilog-HDL test-module imported from the ‘XADC_Display_SV_2019’ project requires modification for use with the top-level module developed in Task 4.2. 

The main changes are as follows: 

i. Add identically named declarations of input and output signals for the ‘TxSysRTL’ and ‘RxSysRTL’ modules along with the ‘Auto_Man’ selection input (use type logic). ii. Add a continuous assignment to connect the transmitter output to the receiver input,  ‘TxOut’ to ‘RxIn’, thereby creating the ‘loop-back’ test. 

iii. Add sequential statements to the initial block shown below, to create the stimulus required to show correct automatic and manual transmission across the link, using the waveform extract shown in figure 8.

 

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  • Posted on : December 31st, 2018

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