University : University of New South Wales UniLearnO is not sponsored or endorsed by this college or university.
Subject Code : ELEC2141
Country : Australia
Assignment Task:

Task:

Question 1. (50 marks) i) Consider the following Boolean function F: F(A,B,C,D) =

a) Assuming that F is implemented using the basic logic gates, find the total gate input cost of the realization. [2.5 mark]

b) Draw the truth table for the function F. [5 marks]

c) Express the function F as a Sum-of-Minterms (you may use the “little m” short cut notation). [5 marks]

d) Express the function F as a Product-of-Maxterms ( you may use the “big M” short-cut notation) [5 marks]

e) Using a Karnaugh map, express the function as a minimal Sum-of-Products. List all prime implicants and essential prime implicants. [7.5 marks]

f) Using a Karnaugh map, express the function F as a minimal Product-of-Sums. [5 marks]

g) Using your minimal Sum-of-Products expression from part (e), draw the logic diagram (circuit) using NAND gates only. Assume no complemented signals are available. [5 marks]

h) Apply factoring and decomposition to minimize the Boolean expression in part (e) further and calculate the reduction in the total gate-input cost as compared to the implementation in part (a). [7.5 marks] ii) Using Boolean algebraic manipulation, prove that ???????? + ???????? + ???????? + ???????? = (?????+ ???? + ???? + ????)(???? + ???? + ???? + ????) [7.5 marks] End of paper. - 3 - - 3 - Question 2. (50 marks)

i) Convert (16B4.A) in base 13 number system to a base 6 number system. You may limit the number of digits in the fraction part to three. [7.5 marks]

ii) Suppose you are given a task to design a 9-to-512-line decoder using only two input AND and NOT gates, outline the design procedure you may follow and indicate the total input gate cost of your design. [7.5 marks]

iii) You are to design a combinational circuit with three data inputs: D2, D1, D0; two control inputs: C1 and C0, and two outputs: R1 and R0.R1 and R0 should be the remainder after dividing the binary number formed from D2, D1, D0 by the number formed by C1, C0. Note that division by zero will never be requested. [ For example, if D2,D1,D0 = 111 and C1,C0 =10, then R1, R0 = 01; that is, the remainder of 7 divided by 2 is 1]

a) Briefly describe the design approach you may follow. [5 marks]

b) Based on your approach in (a), implement your design only for R1. [10 marks]

c) Implement your design only for R1 using at least one functional block ( decoder, multiplexer etc) and any number of logic gates of your choice. [10 marks] d) Implement your design for R1 using only XOR and AND logic gates. Inverters are not available.

This ELEC2141 : Engineering   Assignment has been solved by our Engineering Experts at Online Assignment Bank. Our Assignment Writing Experts are efficient to provide a fresh solution to this question. We are serving more than 10000+ Students in Australia, UK & US by helping them to score HD in their academics. Our Experts are well trained to follow all marking rubrics & referencing style.

Be it a used or new solution, the quality of the work submitted by our assignment experts remains unhampered. You may continue to expect the same or even better quality with the used and new assignment solution files respectively. There’s one thing to be noticed that you could choose one between the two and acquire an HD either way. You could choose a new assignment solution file to get yourself an exclusive, plagiarism (with free Turnitin file), expert quality assignment or order an old solution file that was considered worthy of the highest distinction.

  • Uploaded By : admin
  • Posted on : March 20th, 2019
  • Downloads : 0

Whatsapp Tap to ChatGet instant assistance