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EE5511: Design and Evaluation of an Error Control Codec - Engineering Assignment Help

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Added on: 2020-08-22 04:49:40
Order Code: MAS32653
Question Task Id: 175233
Assignment Task:

Learning Outcomes
After the assessment, the students should have a clear view of
1. the operation of a codec in communication systems
2. the capabilities and restrictions of linear block Hamming codes
3. the design issues involved in the encoder and decoder stage of an error control codec
4. the basic functionality offered by the QUARTUS II simulation tool

TASKS: You are required to complete the following Tasks
Task 1
Design the encoder for a (6,3) Hamming single error-correcting codec using the “interleaved” [P1P2D1P3D2D3] format. You can implement your parity generation using XOR gates. Simulate your circuit to check for correct operation.
Task 2
Design the decoder for a (6,3) Hamming single error-correcting codec using the “interleaved”[P1P2D1P3D2D3] format. You can use a 3-to-8 line decoder for syndrome decoding and XOR gates for the controlled inversion. Employing an appropriate design, simulate your circuit to check for correct operation.
Task 3
Analyze the performance of the CODEC. Join your encoder to the decoder and add an XOR gate with an ‘input’ in each bit transmission line to allow you to introduce errors into the transmission. Simulate your circuit and check that it can cope with the six single errors as expected.
Task 4
By experimenting with your implemented codec, examine the effect, in terms of additional errors, of (i) all 15 double errors, (ii) all 20 triple errors, (iii) all 15 quadruple errors, (iv) all 6 quintuple errors, (v) the single sextuple error. Note. You only need to consider one of the 8 possible input data words. Why?

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  • Uploaded By : Mia
  • Posted on : August 22nd, 2018
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